Semiconductor devices are liable to defects in circuitry, and these detects increase in proportion to the integration density of the semiconductor device. In order to ensure the reliability of semiconductor devices, it is well knows in the art to screen for detective circuits by performing a burn-in test prior to shipping. This burn-in test drives the internal circuit in an operating condition, but is performed under conditions of stress, i.e., maintaining that device at a high temperature and voltage, in order to ferret out the defects in the circuitry prior to shipment. Specifically, a burn-in test applies a voltage to the device while maintaining that device at a high temperature.
In such burn-in tests the devices are mounted in respective suitable sockets on boards, placed in an oven and heated to a selected temperature which is usually substantially higher than the highest recommended operating temperature of the devices and, while being heated, are repetitively electrically cycled, i.e., powered up or on and then powered down or off. In each such power cycle when the device is turned on, it is tested for failures therein. For example, in a memory device, while powered up, each cell therein would be written and read once and any failures, either read or write would be identified and located.
Typical state of the art burn-in tests, are taught, for example, in U.S. Pat. No. 5,294,776, issued to Tohru Furuyama on Mar. 15, 1994, and U.S. Pat. No. 5,461,328, issued to Devereaux et al. on Oct. 24, 1995. In both these patents the devices, under test, are stimulated and tested only once during the power on portion of each power cycle. Because an adequate test requires that each unit be tested a minimum number of time, a complete burn-in test requires many such power cycles and thus these tests are quite lengthy. Because of their length, such burn-in tests add significantly to the total manufacturing cost of the devices. Thus it is very desirable to reduce the length of these tests for by so doing the manufacturing cost of the devices can be subsequently reduced.
Thus semiconductor devices, such as Random Access Memories (RAMs), and logic units, such as Application Specific Integrated Circuits (ASICs), and Microprocessors, utilized in computers for the storage and retrieval of data computations and etc., are required by JEDEC (Joint Electron, Device and Engineering Council) to be subjected to such burn-in tests. These memories and logic units will herein after be referred to as CMOS devices.
One attempt to reduce this burn-in cost was to increase the size of the burn-in board and thus increase the number of devices being tested during each power on portion of each power cycle. It was found, however that such an increase in the size of the burn-in boards required the use of even longer burn-in clock cycles, which further increased the duration of the burn-in to maintain the same number of stress cycles. These long, burn-in clock cycles adequate for stressing static CMOS logic, present an efficiency problem for high performance self-resetting CMOS circuitry.
For example, in the case of static CMOS SRAM circuits, the power cycle of the array's periphery devices follows the system clock which, for example, is 6 nanoseconds. By periphery devices is meant those devices that form the array support circuits, such as the sense amplifiers, and etc. This means, in such a static CMOS circuit, the periphery devices will be active, i.e., powered on for 3 nanoseconds, during the first half of the system or external clock cycle time and inactive, i.e., in the reset or power off mode, for 3 nanoseconds, i.e., the second half of the system clock cycle time. Thus, in a burn-in situation the SRAM's periphery devices are evenly stressed. This remains constant regardless of the duration of the system clock cycle time. For example, in a burn-in test, if the system clock has a cycle time of 200 nanoseconds (as typically required for proper burn-in operation) then all the periphery devices in the module continue to be evenly stressed, for in this case the periphery devices of the module will remain active for the first half of the system clock cycle (100 nanoseconds) and will be inactive, in the reset mode, for the second half of the system clock cycle (100 nanoseconds).
However, for a self-resetting CMOS circuit, using present day technologies, the length of time that the periphery devices are active is determined not by the system clock cycle time but by a delay built in the self-resetting CMOS circuit. Thus the time the self-resetting CMOS circuit array devices are active is independent of the duty cycle of the system clock. For example, if we assume the delay time of the self-resetting CMOS array is two nanoseconds and again assume that the cycle of the system clock is six nanoseconds, then the self-resetting CMOS circuit array devices will be active or powered on for only two nanoseconds during the three nanosecond first half of the system clock cycle time and inactive, i.e., in the reset or power off mode, for four nanoseconds, i.e., one nanosecond of the first half of the system clock cycle time and the entire 3 nanosecond second half of the system clock cycle time. However with a lengthened system clock cycle time of 200 nanoseconds, as typically required for a proper burn-in operation, the periphery devices of these self-resetting CMOS circuits will still only be on or active for 2 nanoseconds, and will be in the reset or off mode, and thus inactive, for 198 nanoseconds. This remains true even though such periphery devices are capable of running up to one-hundred times faster. Such an imbalance between the active and inactive times of the periphery devices of the self-resetting CMOS circuit does not properly stress the periphery devices of the self resetting CMOS circuit and thus it is necessary to increase the total burn-in time. However to achieve parity of burn-in stressing between self-resetting CMOS circuits and static CMOS circuits is cost prohibitive because of the long times that would be required.
The inefficiency inherent in burn-in stressing of devices, such as self-resetting circuits, with such a short active time and a long reset time has remained a severely limiting factor in achieving adequate burn-in testing of self-resetting CMOS circuits and remains a significant cost of production of such self-resetting CMOS circuits.
One method that has been proposed to overcome this burn-in efficiency problem is to disable the circuit's self-resetting path during burn-in and provide a separate clock input and additional logic to allow the self-resetting circuit to behave as a static CMOS circuit. However, this requires additional logic circuits in each circuit to be tested thereby increasing circuit complexity and circuit cost while requiring a special clock network.
It is thus desirable that a new method be developed whereby such test times can be shortened by a factor of four or more thus reducing the cost of such tests, while maintaining maximum efficiently and a low duty cycle.
The present invention overcomes the above described problems encounted in the burn-in testing of a self-resetting CMOS circuit and achieves increased efficiency in such burn-in testing, without requiring additional logic at each circuit stage, by causing such self-resetting CMOS circuit to self reset multiple times during the active portion of the burn-in clock cycle, i.e., while the system burn-in chamber clock is high, thereby permitting the input data to cycle through the CMOS circuit multiple times thereby increasing the number of times the circuits are stressed in the active region during the burn-in clock cycle.